The present disclosure is related to memory, such as, coherency protocols for memory.
As is well known, a cache stores information, such as, data and coherency state, for a computer or computing system in order to decrease data retrieval times for a processor.
For systems incorporating multi-threaded processor and/or multiple processing devices, the multiple threads and/or multiple processors may often times need to share data stored within the system. The system needs to insure that a thread or processor accesses the most recent and up-to-date data or coherency state information and also to insure that a thread or processor does not access and modify data associated with another thread or processor. Thus, in multi-threaded processors and/or multi-processor systems, cache coherency protocols are utilized for synchronization of information written from, or read into, the cache memory. Furthermore, the cache coherency protocol insures that the information from the cache that is accessed by a thread or processor is the most recent copy of the information.
A typical cache coherency protocol is a directory based cache coherency protocol that utilizes multiple bits to designate a directory and register the respective owner(s) or sharers of the information. However, storage of several bits for each directory is inefficient and costly and precludes the use of directory based coherency protocols for large systems incorporating multiple processors.